Planar lightwave circuits comprise fundamental building blocks for the modern fiber optic communications infrastructure. Planar lightwave circuits are generally devices configured to transmit light in a manner analogous to the transmission of electrical currents in printed circuit boards and integrated circuit devices. Examples include arrayed waveguide grating devices, integrated wavelength multiplexers/demultiplexers, optical switches, optical modulators, wavelength-independent optical couplers, and the like.
Planar lightwave circuits generally involve the provisioning of a series of embedded optical waveguides upon a semiconductor substrate (e.g., silicon), with the optical waveguides fabricated from one or more silica layers formed on the underlying semiconductor substrate. Fabrication techniques required for manufacturing planar lightwave circuits using silica are generally well known.
Prior art FIG. 1 shows a cross-section view of two planar optical waveguides of a conventional PLC. As depicted in FIG. 1, the planar optical waveguides include two doped SiO2 glass cores 10a–10b formed over a SiO2 bottom cladding layer 12 which is on a silicon substrate 13. A SiO2 top cladding layer 11 covers both the cores 10a–b and the bottom cladding layer 12. As described above, the refractive index of the cores 10a–b is higher than that of top cladding layer 11 and the bottom clad 12. Consequently, optical signals are confined axially within cores 10a–b and propagate lengthwise through cores 10a–b. 
There are a number of problems with the prior art fabrication process for the PLC shown in FIG. 1. One problem is the formation of crystallization areas within top cladding layer 11. Crystallization areas tend to form in the low density areas of the top cladding layer. Such low density areas are typically found in the high aspect ratio gaps, such as the gap between cores 10a–b. 
Top cladding layer 11 is typically an SiO2 layer doped with a Phosphorus dopant and a Boron dopant (e.g., BPSG). Those two dopants decrease the re-flow temperature of BPSG and able to adjust the refractive index such that it matches the refractive index of bottom cladding layer 13. The problem is the fact that during the PECVD (plasma enhanced chemical vapor deposition) process for top cladding layer 11, the top cladding layer material deposited between cores 10a–b tends to form seams or voids. To overcome this problem, top cladding layer 11 is gradually built-up through a number of deposition and anneal cycles. This gradual top cladding layer build up process can fill the gap between cores 10a–b without forming voids, however, there are often low density areas in such gaps, where the material of top cladding layer 11 is less dense than in other areas. These low density areas lead to the formation of crystals. The Phosphorus and Boron dopants form BPO4 crystals in the low density areas of the silica matrix.
Prior art FIGS. 2A and 2B show a side cutaway photograph of waveguide cores 20, top cladding layer 21, and BPO4 crystallization areas 22. FIG. 2A shows a case where there is a two micron gap between cores 20. FIG. 2B shows a case where there is a four micron gap between cores 20. The BPO4 crystals between cores 20 can significantly degrade the performance of the PLC, and particularly, active devices such as coupler PLCs wherein the geometry (e.g., the distance between cores 20) and the material properties of top cladding layer 21 between cores 20 are critical to the performance of the coupler.
Prior art FIG. 3 shows a top-down view of a coupler PLC. As depicted in FIG. 3, cores 10a–b form a coupling region wherein the distance between cores 10a–b and the material properties (e.g., consistent refractive index, uniformity, etc.) of the top cladding layer need to be precisely controlled. The top cladding layer between cores 10a–b in the coupling region needs free of crystallization.
A second problem is refractive index control of the top cladding layer. As multiple lots of PLC devices are fabricated, it is difficult to maintain a consistent refractive index across the lots. Prior art BPSG top cladding layers are very sensitive with respect to anneal temperature and the Boron and Phosphorus dopant ratios. As described above, multiple deposition and anneal cycles are required to fill the high aspect ratio gaps. For example, there are typically at least six deposition/anneal cycles for top clad deposition for arrayed waveguide grating PLCs. Active PLC devices require at least seven top clad deposition/anneal cycles. The multiple deposition/anneal cycles introduce more thermal impacts on the cores (e.g., which can cause core deformation and shrinkage) and on the first few layers of the top clad. The multiple high temperature anneal cycles makes the refractive index hard to control due to migration of Phosphorus atoms. Additionally, high anneal temperatures require an extra 10 percent phosphorus dopant gas flow (e.g., PH3) to place top clad refractive index within the correct range. This high phosphorus concentration in BPSG is the major source of refractive index variation from lot to lot.
A third problem is the fact that the large number of deposition/anneal cycles reduces the yield of the PLC device fabrication process. As described above, to reduce crystallization problems, six or more deposition/anneal cycles are used for AWG devices and seven or more deposition/anneal cycles are used for active PLC devices (e.g., couplers, etc.). The large number of deposition/anneal cycles increases the amount of time required to fabricate the PLC devices.
Thus what is required is a solution that eliminates the formation of crystallization areas within the top cladding layer of a PLC device. What is required is a solution that provides a predictable and stable refractive index for the top cladding layer of a PLC device and renders the refractive index of the top cladding layer less sensitive to variation in the annealing procedure. What is further required is a solution that reduces the number of deposition/anneal cycles required to fabricate AWG PLC devices and active PLC devices. The present invention provides a novel solution to the above requirements.